VLSI Design and Embedded Systems

VLSI Design and Embedded SystemsCHAPTER 1INTRODUCTION1.1 Motivation build wageed curve (PLL) 1-3 is the heart of the many modern electronics as well as communication system. Recently deal of the researches have conducted on the devise of pattern flinged loop (PLL) traffic circle and still research is going on this topic. Most of the researches have conducted to realize a higher lock graze PLL with less(prenominal)er lock condemnation 4 and have tolerable level entropy. The or so versatile application of the phase locked loops (PLL) is for while gene proportionalityn and time recovery in microprocessor, net expireing, communication systems, and absolute oftenness synthesizers. grade locked-loops (PLLs) atomic deed 18 commonly employ to generate timely on-chip quantifys in high- work digital systems. Modern wireless communication systems employ Phase Locked ite dimensionn (PLL) of import(prenominal)ly for synchronization, time synthesis, skew and jitter reduc tion 5. Phase locked loops experience wide application in several(prenominal) modern applications mostly in advance communication and instrumentation systems. PLL being a mixed channelise perimeter involves human body ch separately(prenominal)enge at high frequence.Since its inspection in early 1930s, where it was employ in the synchronization of the horizontal and vertical scans of television, it has come to an advanced homunculus of co-ordinated racing overlap (IC). Today nominate uses in many other applications. The jump PLL ICs were available around 1965 it was built using purely running(a) comp atomic number 53nt. Recent advances in integrated circuit excogitation proficiencys have led to the development of high implementation PLL which has become more economical and reliable. Now a whole PLL circuit can be integrated as a part of a larger circuit on a single chip. on that point be in the first place five blocks in a PLL. These be phase relative frequency det ector (PFD), management affection (CP), low pass loop filter (LPF), voltage controlled oscillator (VCO) and frequency divider. Presently almost all in all communication and electronics devices extend at a higher frequency, so for that purpose we hold a hurrying fix PLL. So on that point be a lot of challenges in conception the mentioned different blocks of the PLL to operate at a higher frequency. And these challenges motivated me towards this research topic. In this work mainly the faster locking of the PLL is concentrated by properly choosing the circuit architectures and disputations. The optimization of the VCO circuit is also carried by in this work to get a better frequency precision.1.2 Organization of ThesisBefore going into the details of the PLL, the penury behind this work is mentioned in the Chapter 1 of the thesis. Chapter 2 briefly describes the whole PLL system. An introduction to the PLL circuit is mentioned in the section 2.1. voice 2.2 contains the detail architecture of the whole PLL system. Different types of PLLs ar mentioned in the section 2.3. discussion section 2.4 explains the basic terms utilise in the PLL system while the consecutive sections give the details somewhat the noise and application of the PLL.Chapter 3 builds the concepts of optimization. Definition of optimization technique and different circuit optimization techniques are presented in section 3.1 and 3.2 complianceively. Section 3.3 gives the brief outline of the concept of nonrepresentational programming and convex optimization. The optimization of the CSVCO circuit is explained in section 3.4.The design and synthesis of the PLL is described in Chapter 4. The different design environments used in this work is mentioned in the section 4.1. The earned design procedure is explained in section 4.2. Section 4.3 gives the design specifications and parameters of the work.The simulation declarations of the different circuits used in the PLL are depicte d in the different sections of the Chapter 5. The public presentation of the CSVCO knowing using convex optimization is compared with that of the traditional rule in section 5.3. Section 5.5 gives the different simulation results of the PLL and its accomplishment comparison in the midst of formal and post layout level. At last Chapter 6 provides the expiry that inferred from the work.CHAPTER 2PHASE LOCKED LOOP2.1 IntroductionA PLL is a closed-loop feedback system that primed(p)s fixed phase kindred between its takings quantify phase and the phase of a propagation clock. A PLL is capable of trailing the phase changes that falls in this bandwidth of the PLL. A PLL also multiplies a low-frequency reference clock CKref to produce a high-frequency clock CKout this is known as clock synthesis.A PLL has a negative feedback control system circuit. The main heading of a PLL is to generate a place in which the phase is the same as the phase of a reference charge. This is achiev ed after many iterations of comparison of the reference and feedback guides. In this lock mode the phase of the reference and feedback signal is zero. After this, the PLL continues to compare the two signals unless since they are in lock mode, the PLL turnout is incessant.The basic block diagram of the PLL is shown in the Figure 2.1. In general a PLL consists of five main blocksPhase sensor or Phase Frequency Detector (PD or PFD)Charge Pump (CP) touch off Pass Filter (LPF) emf Controlled Oscillator (VCO)Divide by N CounterThe Phase frequency Detector (PFD) is one of the main parts in PLL circuits. It compares the phase and frequency difference between the reference clock and the feedback clock. Depending upon the phase and frequency deviation, it generates two end product signals UP and DOWN. The Charge Pump (CP) circuit is used in the PLL to combine both the yields of the PFD and give a single output. The output of the CP circuit is fed to a Low Pass Filter (LPF) to generate a DC control voltage. The phase and frequency of the Voltage Controlled Oscillator (VCO) output depends on the generated DC control voltage. If the PFD generates an UP signal, the error voltage at the output of LPF increases which in turn increase the VCO output signal frequency. On the contrary, if a DOWN signal is generated, the VCO output signal frequency decreases. The output of the VCO is whence fed back to the PFD in order to recalculate the phase difference, and then we can create closed loop frequency control system.2.2 PLL ArchitectureThe architecture of a charge- kernel PLL is shown in Figure 2.2. A PLL comprises of several instalments. They are (1) phase or phase frequency detector, (2) charge pump, (3) loop filter, (4) voltage-controlled oscillator, and (5) frequency divider. The functioning of each block is briefly explained below.2.2.1 Phase Frequency DetectorThe Phase frequency Detector (PFD) is one of the main part in PLL circuits. It compares the phase and frequ ency difference between the reference clock and the feedback clock. Depending upon the phase and frequency deviation, it generates two output signals UP and DOWN. Figure 2.3 shows a traditional PFD circuit.If there is a phase difference between the two signals, it go away generate UP or DOWN synchronized signals. When the reference clock insurrection environ leads the feedback enter clock rising march on UP signal goes high while keeping DOWN signal low. On the other strive if the feedback input clock rising edge leads the reference clock rising edge DOWN signal goes high and UP signal goes low. Fast phase and frequency acquisition PFDs 6-7 are generally pet over traditional PFD.2.2.2 Charge Pump and Loop FilterCharge pump circuit is an important block of the whole PLL system. It transmutes the phase or frequency difference information into a voltage, used to song the VCO. Charge pump circuit is used to combine both the outputs of the PFD and give a single output which is fed to the input of the filter. Charge pump circuit gives a constant stream of comfort IPDI which should be insensitive to the supply voltage variation 8. The amplitude of the current always remains same but the polarity changes which depend on the value of the UP and DOWN signal. The ceremonious diagram of the charge pump circuit with loop filter is shown in the Figure 2.4.When the UP signal goes high M2 junction transistor turns ON while M1 is OFF and the output current is IPDI with a positive polarity. When the down signal becomes high M1 transistor turns ON while M2 is OFF and the output current is IPDI with a negative polarity. The charge pump output current 3 is attached byIPDI=IPUMPIPUMP4=2IPUMP4=IPUMP2=KPDI (1)Where KPDI=IPUMP2 (amps/radian) (2)The passive low pass loop filter is used to convert back the charge pump current into the voltage. The filter should be as compact as contingent 9.The output voltage of the loop filter controls the oscillation frequency of the VCO. The loop filter voltage will increase if Fref rising edge leads Fin rising edge and will decrease if Fin rising edge leads Fref rising edge. If the PLL is in locked state it maintains a constant value.The VCO input voltage is given byVinvco = KF IPDI (3)Where KF is the straighten out of the loop filter.2.2.3 Voltage Controlled OscillatorAn oscillator is an autonomous system which generates a periodic output without any input. The most popular type of the VCO circuit is the current starved voltage controlled oscillator (CSVCO). Here the number of inverter stages is fixed with 5. The modify view of a single stage current starved oscillator is shown in the Figure 2.5.Transistors M2 and M3 operate as an inverter while M1 and M4 operate as current sources. The current sources, Ml and M4, limit the current available to the inverter, M2 and M3 in other words, the inverter is starved for current. The desired c inject frequency of the designed circuit is 1GHz with a supply of 1.8V. T he CSVCO is designed both in usual manner as mentioned in 3, 10, 11. The general circuit diagram of the current starved voltage controlled oscillator is shown in the Figure 2.6.To determine the design equations for the CSVCO, consider the simplified view of VCO in Figure 2.5. The total capacitance on the drains of M2 and M3 is given byCtot=52Cox(LpWp+LnWn) (4)The time it takes to charge Ctot from zero to VSP with the constant current ID4 is given byt1=VSPID4Ctot (5)While the time it takes to discharge Ctot from VDD to VSP is given byt1=VDD-VSPID1Ctot (6)If we set ID4= ID1=ID then the sum of t1 and t2 is given byt1+t2=VDDIDCtot (7)The oscillation frequency of CSVCO for N number of stage isfosc=1Nt1+t2=IDNCtotVDD (8)This is equal to fcenter when Vinvco=VDD2 (9)The gain of the VCO is given byKVCO=fmax-fminVmax-Vmin HzV (10)2.2.4 Frequency DividerThe output of the VCO is fed back to the input of PFD through the frequency divider circuit. The frequency divider in the PLL circuit forms a closed loop. It scales down the frequency of the VCO output signal. A simple D flip flop (DFF) acts as a frequency divider circuit. The schematic of a simple DFF groupd divide by 2 frequency divider circuit is shown in the Figure 2.7.2.3 Types of PLL at that place are mainly 4 types of PLL are available. They are. Liner PLLDigital PLL on the whole Digital PLLSoft PLL2.4 Terms in PLL2.4.1 Lock in RangeOnce the PLL is in lock state what is the effigy of frequencies for which it can keep itself locked is called as lock in range. This is also called as track range or holding range.2.4.2 Capture RangeWhen the PLL is initially not in lock, what frequency range can make PLL lock is called as capture range. This is also known as acquisition range. This is straightway proportional to the LPF bandwidth. Reduction in the loop filter bandwidth so improves the rejection of the out of band signals, but at the same time the capture range decreases, pull in time becomes larger and phase rim b ecomes poor.2.4.3 Pull in TimeThe total time taken by the PLL to capture the signal (or to get the lock) is called as Pull in Time of PLL. It is also called as Acquisition Time of PLL.2.4.4 Bandwidth of PLLBandwidth is the frequency at which the PLL begins to lose the lock with reference.2.5 Noises in PLLThe output of the hardheaded system deviates from the desired response. This is because of the imperfections and noises in the system. The supply noise also affects the output noise of the PLL system 12. There are mainly 4 types of noises. They are explained below.2.5.1 Phase NoiseThe phase fluctuation due to the random frequency variation of a signal is called as phase noise. This is mostly affected by oscillators frequency stpower. The main sources of the phase noise in PLL are oscillator noise 12-15, PFD and frequency divider circuit. The main chemical elements of the phase noise are thermal and flicker noise.2.5.2 JitterA jitter is the short term-term variations of a signal wi th respect to its ideal position in time 16-19. This riddle negatively impacts the info transmission quality. Jitter and phase noise are closely related and can be encipherd one from another 18. Deviation from the ideal position can occur on either leading edge or trailing edge of signal. Jitter may be induced and coupled onto a clock signal from several different sources and is not uniform over all frequencies. Excessive jitter can increase routine error rate (BER) of communication signal 19. In digital system Jitter leads to violation in time margins, causing circuits to behave improperly.2.5.3 SpurNon-desired frequency content not related to the frequency of oscillation and its harmonics is called as Spur. There are mainly two types of spur. They are reference spur and fractional spur. mention spur comes into picture in an integer PLL while fractional spur plays a major section in fractional PLL. When the PLL is in lock state the phase and frequency inputs to the PFD are es sentially equal. There should not be any error output from the PFD. Since this can create fuss, so the PFD is designed such(prenominal) that, in the locked state the current pulses from the CP will have a very narrow width as shown in the Figure 2.9. Because of this the input control voltage of the VCO is modulated by the reference signal and thus produces Reference Spur 20.2.5.4 Charge Pump Leakage CurrentWhen the CP output from the synthesizer is programmed to the high ohmic resistance state, in practice there should not be any current flow. But in operable some outpouring current flows in the circuit and this is known as charge pump leakage current 20.2.6 Applications of PLLThe demand of the PLL circuit increases day by day because of its wide application in the playing field of electronics, communication and instrumentation. The recent applications of the PLL circuits are in memories, microprocessors, hard disk drive electronics, RF and wireless transceivers, clock recovery circuits on microcontroller boards and optical fiber receivers. Some of the PLL applications are mentioned below.1. Frequency SynthesisA frequency synthesizer is an electronic system for generating a range of frequencies from a single fixed time base or oscillator.2. Clock GenerationMany electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the measure supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or nose candy MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple GHz and the reference crystal is just tens or hundreds of megahertz.3. Carrier recuperation (Clock Recovery)Some data streams, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive), are sent without an accompanying clock. The receiver generat es a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a PLL. This process is referred to as clock recovery.4. SkewReductionThis is one of the very popular and earliest uses of PLL. Suppose synchronous pair of data and clock lines enter a large digital chip. Since clock typically drives a large number of transistors and logic interconnects, it is first applied to large buffer. Thus, the clock distributed on chip may suffer from substantial skew with respect to data. This is an undesirable effect which reduces the timing budget for on-chip operations.5. Jitter and Noise ReductionOne desirable property of all PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the static phase offset. The variance between these phases is called tracking jitter. Ideally, the static phase offset s hould be zero, and the tracking jitter should be as low as possible.CHAPTER 3CONVEX OPTIMIZATION OF VCO IN PLL3.1 What is an optimization technique?Optimization technique is nothing but the determination of the action that optimizes i.e. minimizes or maximizes the result of the object function. Optimization technique is applied to the circuits aiming at finding out the optimized circuit design parameter to achieve either the best performance or the desired performance. Optimization techniques are a set of most powerful tools that are used in efficiently handling the design resources and there by achieve the best result. Mainly optimization techniques are applied to the circuit for the selection of the component values, devices sizes, and value of the voltage or current source.3.2 Types of circuit optimization methodThere are mainly quartet types of circuit optimization methods exist. They areClassical optimizationKnowledge based optimizationGlobal optimization method gibbose opti mization and geometric programming3.2.1 Classical Optimization MethodsIn case of elongate circuit CAD, classical optimization methods 21, such as steepest descent, sequential quadratic programming, and Lagrange multiplier methods are mainly used. These methods are used with more complicated circuit models, including so far full SPICE simulations in each iteration. This method can handle a wide variety of problem. For this there is a need of a set of performance measures and computation of one or more derivatives. The main disadvantage of the classical optimization methods is that the global optimal solution is not possible. This method pass outs to find a feasible design even one exist. This method gives only the local minima instead of global solution. Since many different initial designs are considered to get the global optimization, the method becomes slower. Because of the human intervention (to give good initial designs), the method becomes less automated. The classical met hods become slow if complex models are used.3.2.2 Knowledge-Based MethodsKnowledge-based and expert-systems methods such as genetic algorithm or evolution systems, systems based on Fuzzy logic, and heuristics-based systems have also been widely used in linear circuit CAD 21. In case of knowledge based methods, there are few limitations on the types of problems, specifications, and performance measures that are to be considered. These methods do not require the computation of the derivatives. This is not possible to find a global optimal design solution using these methods. The final design is decided on the basis of the initial design chosen and the algorithm parameters. The disadvantage of the knowledge based methods is that they simply fail to find a feasible solution even when one may exist. There is a need of human intervention during the design and the training process.3.2.3 Global Optimization MethodsGlobal optimization methods such as branch and margin and simulated anneali ng are also used in analog circuit design 21. These methods are guaranteed to find the global optimal design solution. The global optimal design is opinionated by the branch and bound methods unambiguously. In each iteration, a suboptimal feasible design and also a lower bound on the achievable performance is maintained by this method. This enables the algorithm to terminate non-heuristically, i.e., with have it away confidence that the global design has been found within a given tolerance. The branch and bound method is extremely slow, with computation growing exponentially with problem size. The trapping in a locally optimal design can be avoided by using simulated annealing (SA). This method can compute the global optimal solution but not guaranteed. Since there is no real-time lower bound is available, so termination is heuristic. This method can also handle a wide variety of performance indices and objects. The main advantage of SA is that it handles the continuous variables and discrete variables problems efficiently and reduces the chances of getting a non-globally optimal design. The only problem with this method is that it is very slow and can not guarantee a global optimal solution.3.2.4 Convex Optimization and Geometric Programming MethodsGeometric programming methods are special optimization problems in which the objective and constraint functions are all convex 22-24. Convex optimization technique can solve the problems having a large number of variables and constraints very efficiently 22. The main advantage of this method for which people generally adopt is that the method gives the global solution. Infeasibility is unambiguously detected. Since a lower bound on the achievable performance is given, so the method uses a completely non- heuristic stopping criterion.3.3 Geometric programming and convex optimizationGeometric programming is a special type of optimization technique in which all the objective must be convex. Before applying this tech nique it has to confirm that whether the given problem is convex optimization problem or not. Convex optimization problem means the problem of minimizing a convex function root to convex inequality constraints and linear equality constraints. In IC integration convex optimization and geometric programming has become a more efficient computational tool for optimization purpose. This method has an ability to handle thousands of variables and constraints and solve efficiently. The main advantage of convex optimization technique is that it gives the global optimized value and the naughty design. The fact that geometric programs can be solved very efficiently has a number of practical consequences. For example, the method can be used to simultaneously optimize the design of a large number of circuits in a single large mixed-mode integrated circuit. The designs of the individual circuits are coupled by constraints on total power and area, and by various parameters that affect the circui t coupling such as input capacitance, output resistance, etc. Convex optimization is used to find out the optimized value of these parameter and sizing of the devices in the circuit 25. Another application is to use the efficiency to obtain robust designs i.e., designs that are guaranteed to come over a set of specifications over a variety of processes or technology parameter values. This is done by simply replicating the specifications with a (possibly large) number of representative process parameters, which is practical only because geometric programs with thousands of constraints are readily solved. A real valued function fx defined on an interval (space) is called convex ifftx1+1-tx2tfx1+1-tfx2 (11)For every t,0In the Figure 3.1 function fx is represented as a convex function on an interval.The convex optimization problem is in the form of minimize f0xSubjected to fix1 , i=1, 2, 3, mgix=1 , i=1, 2, 3, pxi1 , i=1, 2, 3, nWhere fix is a posynomial functiongix is a monomial func tionLet x1,x2xn be n real positive variables. We can denote the vector (xi,xi.xi) of these variables asx. A function f is called a posynomial function of x if it has the formfix1,x2xn=k=1tCkx11kx22k..xnnk (12)Where Cj0 and ij R. The coefficients Cj must be nonnegative but the exponents ij can be any real numbers including negative or fractional. When there is exactly one nonzero term in the sum i.e. t=1 and C10, we call f is a monomial function.3.3.1 Advantages Handle thousands of variables and constraints and solve efficiently. Global optimization can be obtained.3.3.2 Disadvantages* Strictly limited to types of problems, performance specification and objectives that can be handled.3.4 Optimization of the VCO circuitIn my earlier design of the VCO circuit, the sizes of all the five inverter stages are same. Now the convex optimization technique is applied to find out the optimal scaling ratio of the different inverter stages to get the optimal design with a better performance. The re are 5 inverter stages and the design has to give a learn of 100ps. The load capacitance of the VCO circuit is 65 fF. All these design constraints are formulated and applied to the convex optimization technique. Mainly optimization techniques are applied for selection of component values and transistor sizing.In this work I have used the geometric programming technique to find out the optimized scaling ratio of the different stages in CSVCO to meet the desired center frequency with lesser deviation. Let xi is the scaling ration of the ith stage, CL is the load capacitance, and D is the total delay of the inverter stages then optimization problem is in the form ofMinimize sum (xi)Subjected to CLCLmaxDDmaxWhere CLmax and Dmax are required design parameters and has a constant value.CHAPTER 4DESIGN AND SYNTHESIS OF PLL4.1 Design EnvironmentThe schematic level design entry of the circuits is carried out in the CADENCE Virtuoso Analog Design Environment. The layout of the PLL is design ed in Virtuoso XL using GPDK090 library. In order to analyze the performances, these circuits are simulated in the Spectre simulator of CADENCE tool. Different performance indices such as phase noise, power consumption and lock time are measured in this environment. Transient, parametric sweep and phase noise analyses are carried out in this work to find out the performances of the circuit. The optimization of the current starved VCO circuit, the scale factor for transistor sizing is found out using the MATLAB environment.4.2 Design Procedure4.2.1 VCO DesignSince VCO is the heart of the whole PLL system, it should be designed in a proper manner. The design steps for the current starved VCO are as follows. gradation 1Find the value of the propagation delay for each stage of the inverter in the VCO circuit using the following equation.p=1Nf (13)Where p= phl= plh= half of the propagation delay time of the inverterN= no of inverter stagesf= required center frequency of oscillationStep 2 Find the WL ratio for the transistors in the different inverter stages using the equation in below.WL n=CloadphlnCoxVdd-VT,n2VT,nVdd-VT,n+ln4Vdd-VT,nVdd-1 (14)WL p=CloadplhpCoxVdd-VT,p2VT,pVdd-VT,p+ln4Vdd-VT,pVdd-1 (15)Step 3After finding the WL ratio, find the values for W and L.Step 4Find the value of the total capacitance form the expressionCtot=52Cox(LpWp+LnWn) (16)Where Cox is the oxide capacitanceLp,Wp,Ln,Wn is the width and length of the PMOS and NMOS transistors in the inverter stages.Step 5Calculate the value of drain current for the center frequency which is given byIDcenter=NCtotVddf (17)Step 6Find the WL ratio for the current starving transistors in the circuit from the drain current expression which is represented asWL n=2IDcenternCoxVgs-VT,n2 (18)Similarly WL p=2.5WL n (19)4.2.2 Design of Phase Locked LoopThe value of the charge pump current and the component parameters of the loop filter play a major role in the design of the phase locked loop circuit. The value of th e lock time mainly depends upon these parameters. So while designing the circuit proper care should be taken in calculating these parameters. For the given values of reference(Fref) and output frequency(Fout) as well as the lock in range, the following steps to be carried out in designing the filter circuit.Step 1Find the value of the divider circuit to be used which is given byn=FoutFref (20)Step 2Find the value of the natural frequency (n) from the lock in range as given belowlock in range=2n (21)Step 3Find the value of the charge pump gain (KPDI) from the charge pump current used in the circuit which is given byKPDI=Ipump2 (Amps/radian) (22)Step 4Find the value of the gain of the VCO (Kvco) circuit from the characteristics curve using the following expression.Kvco=fmax-fminVmax-Vmin (Hz/V) (23)Step 5Find the values of the loop filter component parameters using the following expressions.C1=KPDIKvcoNn2 (24)C2=C110 (25)R=2nC1 (26)4.3 Design Specifications and contentions4.3.1 VCO D esign SpecificationThe current starved VCO design specifications are mentioned in the following table.Table 1 VCO design specifications4.3.2 VCO Design ParametersTable 2 itemization of design parameters of the CSVCO circuit4.3.3 PLL Design ParametersThe whole PLL system design specifications and parameters are shown in the Table 3.ParameterValueReference frequency((Fref)500 MHzoutput frequency(Fout)1 GHzLock in range100 MHz